Generation Report - NCO Compiler MegaCore Function v2.2.2

Entity NamemyNCO_st
Variation NamemyNCO
Variation HDLVerilog HDL
Output DirectoryC:\Documents and Settings\kh68vt\My Documents\LKH_research\AlterWork\AD2DA_FIR_NCO\NCO_design

File Summary

IP Toolbench is creating the following files in the output directory:
FileDescription
myNCO.vA MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
myNCO_inst.vVerilog HDL sample instantiation file
myNCO.cmpA VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.
myNCO.incAn AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.
myNCO_bb.vVerilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.
myNCO.bsfQuartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.
myNCO_st.vGenerated NCO synthesizable netlist. This file is required for Quartus II synthesis. It will be added to your Quartus II project
myNCO.voVerilog HDL IP Functional Simulation model
myNCO_tb.vVerilog HDL Testbench
myNCO_vo_msim.tclModelsim TCL Script to run the Verilog HDL IP Functional Simulation model and generated Verilog HDL testbench in the Modelsim simulation software
myNCO_wave.doModelsim Waveform File
myNCO_model.mMatlab m-file describing a Matlab bit-accurate model.
myNCO_tb.mMatlab Testbench
myNCO_sin.hexIntel Hex-format ROM initialization file.
myNCO_cos.hexIntel Hex-format ROM initialization file.
myNCO.vecQuartus Vector File.
myNCO.htmlThe MegaCore function report file.

MegaCore Function Variation File Ports

NameDirectionWidth
phi_inc_iINPUT32
fsin_oOUTPUT12
fcos_oOUTPUT12
clkINPUT1
resetINPUT1
clkenINPUT1
data_readyOUTPUT1