ECE: Electrical & Computer Engineering

ECE 4514: Digital Design II

This is the course outline for the Spring 2008 version of Digital Design II.

Lecture 1: Introduction (Slides)

Lecture 2: Hierarchical Design (Slides)

Lecture 3: Verilog Bread and Butter (Slides)

Lecture 4: Gate Level Modeling (Slides)

Lecture 5: How the Verilog Simulator Workds (Slides)

Lecture 6: Random Number Generators (Slides)

Lecture 7: Dataflow Modeling (Slides)

Lecture 8: Multiplexed Datapaths (Slides)

Lecture 9: System Commands and Testbenches (Slides)

Lecture 10: Behavioral Modeling: Non-blocking Assignments (Slides)

Lecture 11: Design of a SHA-1 Module in Verilog (Slides)

Lecture 12: Behavioral Modeling/ Conditionals and Loops (Slides)

Lecture 13: Logic Synthesis (Slides)

Lecture 14: Spartan 3ES500 FPGA (Slides)

Lecture 15: FSM-based Control (Slides)

Lecture 16: Synthesis of Memories in FPGA (Slides)

Lecture 17: Hardware Division (Slides)

Lecture 18: Optimizing Area (Slides)

Lecture 19: Optimizing Performance (Slides)

Lecture 20: Static Timing Analysis (Slides)

Lecture 21: Functions and Tasks (Slides)

Lecture 22: Design Economics (Slides)